Ceramics have found widespread use in electronics as a substrate for integrated circuit packages. Metallized circuit patterns are applied to the ceramic substrate, and ceramic and metallization are co-sintered to create a monolith of substrate and circuitry. Multi-layer circuit packages are constructed by combining ceramic particles and organic binders into unfired, or "green," tape. Inter-layer conductive paths, known as "vias," are then inserted through the layers, forming electrical interconnections between the circuits on each layer after they are stacked and processed. Thereafter, metallized circuit patterns are applied. The tape layers typically have thicknesses ranging from 5 to 25 mils. Holes and notches are formed in the layers as required. Multiple layers of printed tape are stacked and then laminated under pressure, and ceramic and metallization co-sintered to form a monolithic structure with three-dimensional circuitry.
Typically, substrates are formed from a combination of approximately 90-94% commercial, broad size distribution alumina and 6-10% silicon-based glass, and tungsten or molybdenum/manganese paste is used to form the metallized conductive paths. The glass is added to the alumina to promote bonding of the tungsten to the alumina and to provide sintering of the alumina at a lower temperature than for 98+% commercial alumina. Upon co-firing of the alumina and tungsten, the glass component migrates from the alumina layer to the tungsten layer, providing interface adhesion between the paste component and substrate, and promoting bonding. Substrates have typically been formed from particles having a broad size distribution. The prior art suggests that the production of a densely-packed body from particulate material requires the use of a mixture of particles having a broad size distribution. It was thought that a mix of large and small particles was necessary so that small particles would fill the voids between large particles and hence provide maximum packing of particles. Circuit packages produced from prior art formulations typically display a dielectric constant of approximately 9-9.5, thermal conductivity approximately 0.045 cal cm/cm.sup.2 sec .degree.C. at 20.degree. C. (compared with 0.085 cal cm/cm.sup.2 sec .degree.C. for 99.5% alumina), shrinkage variability of 1.0% (0.5% considered optimal at present), and a surface finish of greater than 25 microinches. While these substrate properties may have been acceptable for conventional semiconductor packages, they are inadequate for high-performance large scale integration applications and other specialized applications.
The use of a broad size distribution of particles generally results in non-uniform particle packing within the ceramic tape, which in turn leads to shrinkage variability during the co-firing (sintering) operation. Shrinkage variability exacerbates the problem of meeting critical dimensional tolerances when co-sintering with conductor films. Reducing shrinkage variability is critical for process control and product quality in a broad range of applications, and is especially important as feature size decreases. This is because variability in shrinkage prevents precise location of circuit pads, vias, and other interconnects, and often results in the necessity of rejecting the ceramic circuit packages because of electrical discontinuities between internal interconnects, and, in the case of thin-film applications, additional discontinuities between co-fired metallization and subsequently applied thin-film metallization. A reduction in shrinkage variability from the prior art 1% level would increase product yield, and benefit both the substrate manufacturer and substrate consumer, who, may, for example, require precise positioning of devices and interconnects for reliable post-fire circuit personalization by thin-film metallization.
Surface finish also becomes increasingly important as feature size decreases. In microelectronic circuits produced by thin-film metallization techniques, the conductor thickness can be as small as a few microns (1 micron=40 microinches), so that if the substrate has a 25 microinch surface finish typical of the prior art, the conductor path will have substantial differences in thickness along its length, or may even be discontinuous, with a corresponding degradation of function. Accordingly, roughness of surface finish prevents post-firing circuit personalization by thin-film metallization. The use of a broad size distribution of particles results in a relatively rough surface finish which requires polishing to yield a surface suitable for thin film deposition. Polishing techniques can bring the surface finish to approximately 6-10 microinches, but further improvement through polishing is not possible, because the polishing process plucks larger particles off the surface, leaving voids and increasing porosity. In addition, polishing significantly increases the cost of substrates.
Moreover, porosity of the as-fired surface, especially when combined with surface roughness, leads to the problem of retention of plating salts. Aggressive cleaning procedures are required to avoid deposition of plating where not desired, and to avoid blistering upon firing. Greater smoothness and lack of porosity would allow the use of more active catalysts, which in turn would increase product yield through electroless plating operations.
In addition, an improvement in thermal conductivity would increase heat dissipation and provide a more stable thermal environment for semiconductor devices.
Accordingly, there exists a need for a substrate material with low shrinkage variability, an as-fired surface finish suitable for thin film deposition, and superior thermal characteristics.